1. Field of Invention
The present invention relates to liquid crystal display. More particularly, the present invention relates to a source driver and the driving method for low power applications.
2. Description of Related Art
A liquid crystal display (LCD) has many advantages over other types of displays, and is widely used in various applications such as televisions, mobile phones, video camcorders, personal computers and so on. Image data of the LCD are provided through one or more source drivers.
FIG. 1 is a block diagram depicting a conventional source driver 100 used in an LCD. The source driver 100 has many channels (only one channel is shown in FIG. 1), and each channel has a DAC 102 and an output buffer 104. The DAC 102 selects one gamma voltage from a set of gamma voltages (e.g. V0˜V63) according to all the bits of an N-bit signal (e.g. the bits B0, B1, B2, B3, B4, B5 of a 6-bit signal). The output buffer 104 receives the selected gamma voltage from the DAC 102 and outputs it to an LCD panel 106.
In order to reduce power consumption, the output buffer 104 requires many controls or a complicated class AB amplifier, which may complicate the circuit design or occupy a large chip area. Therefore, it is much desired to provide a low power source driver and the driving method, which only requires a simple circuit design and fewer controls.
FIG. 2 is a block diagram depicting a conventional output buffer 200 used in the source driver 100 of FIG. 1. The output buffer 200 has a PMOS transistor 202, a NMOS transistor 204, a first error amplifier 212 and a second error amplifier 214. The PMOS transistor 202 and the NMOS transistor 204 are electrically connected in series between a high-level voltage (VDDA) and a low-level voltage (VSSA). The gate of the PMOS transistor 202 is electrically connected to the output of the first error amplifier 212, and the gate of the NMOS transistor 204 is electrically connected to the output of the second error amplifier 214. An input voltage (Vin), i.e., the selected gamma voltage from the DAC 102, is input to inverting inputs of the error amplifiers 212 and 214. The non-inverting inputs of the error amplifiers 212 and 214 are electrically connected to each other and coupled to a connection node between the PMOS transistor 202 and the NMOS transistor 204, i.e., the drains of the PMOS transistor 202 and the NMOS transistor 204, to provide an output voltage (Vout) to an LCD panel 222.
With this architecture, the output buffer 200 can occupy a small chip area compared to the widely-used class AB amplifier. However, the error amplifiers may generate an offset voltage of 30 mV or require a complicated circuit design to compensate the offset voltage.